Altium

Design Rule Verification Report

Date: 2/19/2019
Time: 10:31:58 AM
Elapsed Time: 00:00:01
Filename: D:\PCB design\DZC_USB_BOX\USB_pwr_wurth_uni_revB\USB_PWR_WurUni_rev1B.PcbDoc
Warnings: 4
Rule Violations: 0

Summary

Warnings Count
Unplated multi-layer pad(s) detected 4
Total 4

Rule Violations Count
Net Antennae (Tolerance=0mm) (All) 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) 0
Un-Routed Net Constraint ( (All) ) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Width Constraint (Min=0.1mm) (Max=5mm) (Preferred=0.2mm) (All) 0
Clearance Constraint (Gap=0.1mm) (All),(All) 0
Clearance Constraint (Gap=0mm) (OnLayer('GND') And ((IsKeepOut))),(All) 0
Clearance Constraint (Gap=0mm) (OnLayer('BottomLayer') And ((IsKeepOut))),(All) 0
Clearance Constraint (Gap=0mm) (OnLayer('TopLayer') And (IsKeepOut)),(All) 0
Clearance Constraint (Gap=0mm) (OnLayer('PWR') And ((IsKeepOut))),(All) 0
Clearance Constraint (Gap=0.15mm) (OnLayer('PWR') And ((InPoly))),(All) 0
Clearance Constraint (Gap=0.15mm) (OnLayer('BottomLayer') And ((InPoly))),(All) 0
Clearance Constraint (Gap=0.15mm) (OnLayer('TopLayer') And ((InPoly))),(All) 0
Clearance Constraint (Gap=0mm) (InComponent('S2') or InComponent('CN1')),(OnLayer('Keep-Out Layer')) 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Total 0

Warnings

Unplated multi-layer pad(s) detected
Pad Free-0(51mm,2mm) on Multi-Layer on Net GND
Pad Free-0(51mm,20mm) on Multi-Layer on Net GND
Pad Free-0(2mm,2mm) on Multi-Layer on Net R_GND
Pad Free-0(2mm,20mm) on Multi-Layer on Net R_GND

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